MIPS Technologies Targets Multi-CPU SOC Designs With New 32-Bit Processor Core
Small, Flexible, High-Performance MIPS32(TM) M4K(TM) Core Enables SOC Designers to Meet Rapidly Increasing Bandwidth Demands
SAN JOSE, Calif.--(BUSINESS WIRE)--April 29, 2002--
MIPS Technologies, Inc. (Nasdaq: MIPS - news, MIPSB - news), a leading provider
of industry-standard processor architectures and cores for digital
consumer and networking applications, today announced a new 32-bit
synthesizable core designed to optimize SOC designs implemented with
multiple CPU cores.
The emerging trend in multi-CPU SOCs addresses the rapidly
increasing bandwidth requirements in next-generation broadband and
networking devices. The new MIPS32(TM) M4K(TM) core gives designers
higher performance and greater flexibility to achieve higher system
throughput while controlling silicon cost. The flexibility and
re-programmability enables upgrades in software as protocol
specifications or market requirements evolve. Applications for the M4K
core include data plane processing, as well as deeply embedded control
processors, networked storage, residential gateways, set-top boxes and
smart mobile devices.
"Multi-CPU SOCs are required to meet the high-bandwidth demands of
advanced networking equipment," said Linley Gwennap, principal analyst
of The Linley Group. "Modern IC process technology easily supports
many CPUs on a single chip; the problem lies in connecting and
debugging such complex designs. The M4K core provides an efficient and
effective solution to this problem while maintaining compatibility
with the industry-standard MIPS instruction set and tool chain."
The M4K core features a typical clock speed over 300 MHz, yet
minimum power consumption is only 0.10 mW/MHz, and core size is as
small as 0.3 mm2 in 0.13-micron processes. It features code
compression to reduce memory size, and it is the first core to utilize
the MIPS32 architecture enhancements announced last October. These
include bit field instructions for easier handling of packet
information, support for vectored interrupts to decrease interrupt
latency, and multiple register sets for faster context switching.
Multi-CPU designs, in particular, benefit from the core's
high-speed cacheless SRAM interface, user-defined instruction-set
extensions to create highly differentiated features and optimize
performance, and support for easy multi-CPU simulation and debug. For
networking applications, the M4K core is code-compatible with
MIPS-based 64-bit processors in the control plane, which gives
networking system engineers more flexibility to allocate functions
performed by the data plane and control plane processors in order to
boost processing efficiency.
Features
Features of the synthesizable M4K core include:
- Typical performance: 300 MHz, 405 DMIPS (0.13-micron generic
process)
- Optimized cacheless SRAM memory interface that enables
deterministic performance and reduces die size
- 5-stage pipeline that allows most instructions to execute in
one cycle
- Power consumption as low as 0.10 mW/MHz
- Core size as small as 0.3 mm2
- MIPS16e(TM)code compression that reduces memory requirements
by as much as 40 percent
- Packet manipulating bit instructions for packet header and
deep-packet examinations and editing
- Vectored interrupts that reduce latency
- 1, 2 or 4 general-purpose register sets for fast context
switching
- Fast multiply/divide unit
- Enhanced JTAG (EJTAG) with PC and data trace support for easy
multi-CPU debugging
- Seamless, upward compatibility with MIPS64(TM)-based cores
"The M4K core is the first core based on an industry-standard
architecture to have user-defined instruction-set extensions. It is
also the first to include the enhanced MIPS32 architecture, which
offers faster and more flexible packet processing and low-cost
interrupt handling," said Kevin Meyer, vice president of marketing at
MIPS Technologies. "The M4K core also comes with a robust multi-CPU
design environment that enables SOC designers to optimize their
designs and quickly bring them to market."
Comprehensive Support
The M4K core is supported by a rich environment of software and
hardware tools for multi-CPU design and verification. These include
MIPS Technologies' bus-functional model and MIPSsim(TM)
instruction-set simulator, and a complete offering of third-party
development tools.
Availability
The MIPS32 M4K core is available now for licensing. General
availability is scheduled for the third quarter of 2002.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard
processor architectures and cores for digital consumer and network
applications. The company drives the broadest architectural alliance
that is delivering 32- and 64-bit embedded RISC solutions. The company
licenses its intellectual property to semiconductor companies, ASIC
developers and system OEMs. MIPS Technologies and its licensees offer
the widest range of robust, scalable processors in standard, custom,
semi-custom and application-specific products. The company is based in
Mountain View, Calif., and can be reached at +1 (650) 567-5000 or
www.mips.com.
MIPS® is a registered trademark in the United States and other
countries, and MIPS64(TM), MIPS32(TM), M4K(TM), MIPS16e(TM) and
MIPSsim(TM) are trademarks of MIPS Technologies, Inc. All other
trademarks referred to herein are the property of their respective
owners.
Contact:
MIPS Technologies, Inc.
Lee Garvin Flanagin, 650/567-5180
flanagin@mips.com